Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor device comprises a semiconductor substrate, an interlayer insulating layer formed above the semiconductor substrate, a first metal interconnection embedded in the interlayer insulating layer with a surface thereof exposed to the same plane as a surface of the interlayer insulating layer, a diffusion preventive layer formed on at least the first metal interconnection to prevent diffusion of a metal included in the first metal interconnection, a nitrogen-doped silicon oxide layer formed on the diffusion preventive layer, a fluorine-doped silicon oxide layer formed on the nitrogen-doped silicon oxide layer, and a second metal interconnection embedded in the fluorine-doped silicon oxide layer with a surface thereof exposed to the same plane as a surface of the fluorine-doped silicon oxide layer, and electrically connected to the first metal interconnection.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2001-230311, filed Jul.30, 2001, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device andmanufacturing method thereof, and more particularly, to a semiconductordevice employing a fluorine-doped silicon oxide layer as aninterconnection insulating layer, and a method of manufacturing thesame.

[0004] 2. Description of the Related Art

[0005] In prior art semiconductor devices, SiO₂ layer has been used asan insulating layer to electrically isolate interconnections. Such anSiO₂ layer is primarily produced from source gas, for example, silane(SiH₄) and tetraethoxysilane (TEOS) by a low pressure or atmosphericpressure chemical vapor deposition (CVD) technique. Particularly, plasmachemical vapor deposition can produce an SiO₂ layer at a low temperatureof about 400° C., using TEOS and O₂, and the SiO₂ layer produced in thisway has been widely used. Further, as compared with other thin layerproducing methods, the CVD method often uses high purity gas as areaction source, and provides high quality layers.

[0006] However, as microstructure of semiconductor elements has becomewidespread in recent years, concern about reduction of signaltransmission speed has arisen. This implies a problem that reducedinterconnection space increases the capacitance between interconnectionsand reduces signal transmission speed. The reduction in signaltransmission speed seems to be one of the negative factors in increasingthe performance of semiconductor devices. Therefore, to solve theproblem, it is essential to reduce permittivity of the insulating layerformed between interconnections to the lowest possible value.

[0007] To reduce the permittivity, in recent years, fluorine-dopedsilicon oxide or fluorine-doped silicate glass (FSG) has been developedtogether with the parallel plate CVD technique or high density plasmaCVD technique (HDP-CVD). As a method of producing high-density plasma,use of electron cyclotron resonance (ECR) or the inductive coupledplasma (ICP) coil or helicon wave, for example, has been reported.

[0008]FIG. 1 shows a sectional view of Cu multi-layer interconnectionusing a conventional FSG layer. In the same drawing, reference number 81indicates an FSG layer and likewise, 82 indicates a barrier metal layer,83 indicates a Cu interconnection in a lower layer, 84 indicates asilicon nitride layer, 85 indicates an FSG layer, 86 indicates anotherbarrier metal layer, 87 indicates a Cu interconnection of an upperlayer, 88 indicates another silicon nitride layer and 89 indicates asilicon substrate, respectively. The Cu interconnections 83 and 87 aredual damascene interconnections.

[0009] In the FSG layer, as has been reported, the higher the fluorine(F) density, the lower the permittivity, and at the same time, moistureabsorption increases. As the moisture absorption of FSG layers 81 and 85increases, moisture (H₂O) is taken into these FSG layers. And, H causedby the moisture reacts with F contained in these FSG layers, and HF isliberated from the FSG layers 81 and 85.

[0010] Even if moisture is not taken in, HF is produced from H that isinherently contained in the FSG layer 81. Furthermore, HF is alsoproduced by reaction of hydrogen (H) and moisture (H₂O) in siliconnitride layers 84 and 88 with surplus fluorine (F) in FSG layers 81 and85. FSG layers 81 and 85 and silicon nitride layers 84 and 88 contain H,because gaseous materials such as silane and ammonia containing H areemployed as source gas, and this H is mixed into FSG layers 81/85 andsilicon nitride layers 84/88.

[0011] The above-noted HF will cause corrosion of Cu interconnections83/87 or barrier metal layers 82/86, and degrade adhesion between Cuinterconnections 83/87 and insulating layers 81/84/85/88. Further, thiscorrosion and deteriorated adhesion will cause more serious problems,for example, layer peeling off, bonding durability decline and decreasein reliability.

[0012] As described above, it has been proposed to use an FSG layer ininterconnections as an insulating layer with low permittivity, toprevent signal transmission delay. However, there is a problem in usingan FSG layer, that is, moisture absorption is high and HF is generated,causing corrosion of interconnection itself or barrier metal layer orpeeling off of layers. Thus, a semiconductor device employingfluorine-doped silicon oxide as an insulating layer for interconnectionsand including multi-layer interconnection to decrease the influence ofHF, and a method of manufacturing the same have been expected.

BRIEF SUMMARY OF THE INVENTION

[0013] A semiconductor device according to a first aspect of the presentinvention comprises:

[0014] a semiconductor substrate;

[0015] an interlayer insulating layer formed above the semiconductorsubstrate;

[0016] a first metal interconnection embedded in the interlayerinsulating layer with a surface thereof exposed to substantially thesame plane as a surface of the interlayer insulating layer;

[0017] a diffusion preventive layer formed on at least the metalinterconnection to prevent diffusion of a metal included in the firstmetal interconnection;

[0018] a nitrogen-doped silicon oxide layer formed on the diffusionpreventive layer;

[0019] a fluorine-doped silicon oxide layer formed on the nitrogen-dopedsilicon oxide layer; and

[0020] a second metal interconnection embedded in the fluorine-dopedsilicon oxide layer with a surface thereof exposed to substantially thesame plane as a surface of the fluorine-doped silicon oxide layer, andelectrically connected to the first metal interconnection.

[0021] A semiconductor device according to a second aspect of theinvention comprises:

[0022] a semiconductor substrate;

[0023] an interlayer insulating layer formed above the semiconductorsubstrate;

[0024] a first metal interconnection embedded in the interlayerinsulating layer with a surface thereof exposed to substantially thesame plane as a surface of the interlayer insulating layer;

[0025] a diffusion preventive layer formed on at least the metalinterconnection to prevent diffusion of a metal included in the firstmetal interconnection;

[0026] a first nitrogen-doped silicon oxide layer formed on thediffusion preventive layer;

[0027] a fluorine-doped silicon oxide layer formed on the firstnitrogen-doped silicon oxide layer;

[0028] a second nitrogen-doped silicon oxide layer formed on thefluorine-doped silicon oxide layer; and

[0029] a second metal interconnection embedded in the fluorine-dopedsilicon oxide layer with a surface thereof exposed to substantially thesame plane as a surface of the second nitrogen-doped silicon oxidelayer, penetrating through the second nitrogen-doped silicon oxidelayer, and electrically connected to the first metal interconnection.

[0030] A semiconductor device manufacturing method according to a thirdaspect of the invention comprises:

[0031] embedding an under interconnection layer in an interlayerinsulating layer such that a surface thereof is exposed to substantiallythe same plane as a surface of the interlayer insulating layer;

[0032] forming a diffusion preventive layer to prevent diffusion of ametal included in the under interconnection layer, on at least the underinterconnection layer;

[0033] forming a first nitrogen-doped silicon oxide layer on thediffusion preventive layer;

[0034] forming a fluorine-doped silicon oxide layer on thenitrogen-doped silicon oxide layer;

[0035] forming an interconnection groove and a via hole extending from abottom of the interconnection groove above the under interconnectionlayer in the fluorine-doped silicon oxide layer; and

[0036] forming a plug in the via hole with a metal layer, to be inelectrically contact with the under interconnection layer, and an upperinterconnection layer in the interconnection groove with the metallayer, to be electrically contact with the plug.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0037]FIG. 1 is a sectional view of Cu multi-layer interconnectionemploying a conventional FSG layer.

[0038] FIGS. 2A-2F are sectional views illustrating the steps ofmanufacturing Cu multi-layer interconnection in accordance with a firstembodiment.

[0039]FIG. 3 is a perspective view showing a parallel plate CVD systemused for manufacturing the Cu multi-layer interconnection in the firstembodiment.

[0040]FIG. 4A is a sectional view of a conventional multi-layersubstrate not including an SiON layer.

[0041]FIG. 4B is a graph showing a diffusion profile of Si, H, F and Owhen a specimen shown in FIG. 4A is heated in an annealing furnace inatmosphere of N₂ gas at atmospheric pressure.

[0042]FIG. 5A is a sectional view of a multi-layer substrate includingan SiON layer of the first embodiment.

[0043]FIG. 5B is a graph showing a diffusion profile of Si, H, F and Owhen a specimen shown in FIG. 5A is heated in an annealing furnace inatmosphere of N₂ gas at atmospheric pressure.

[0044]FIG. 6 is a graph showing a relationship between a refractiveindex of an SiON layer measured with a He—Ne laser of 633 nm and adiffusion distance of fluorine heated in an annealing furnace inatmosphere of N2 gas at atmospheric pressure.

[0045]FIG. 7 is a graph showing a relationship between a refractiveindex and N composition of an SiON layer.

[0046] FIGS. 8A-8D are sectional views illustrating the steps ofmanufacturing Cu multi-layer interconnection in accordance with a secondembodiment.

DETAILED DESCRIPTION OF THE INVENTION

[0047] Hereinafter embodiments of the present invention will beexplained with reference to the accompanying drawings.

[0048] (First Embodiment)

[0049] FIGS. 2A-2F are sectional views illustrating the steps ofmanufacturing Cu multi-layer interconnection in accordance with a firstembodiment.

[0050]FIG. 2A illustrates in cross section a first Cu interconnectionstructure formed by a known damascene process. The first Cuinterconnection structure comprises a first interlayer insulating layer1 with an interconnection groove on its surface, a first barrier metallayer 2 covering the bottom and sides of the interconnection groove, afirst Cu interconnection (under interconnection layer) 3 embedded in theinterconnection groove, and a first silicon nitride layer 4 formed as aCu diffusion preventive layer on the first interlayer insulating layer1.

[0051] The above first Cu interconnection structure is formed on an Siwafer 13. The interlayer insulating layer 1 is an FSG layer, forexample. In this case, it is desirable to form a nitrogen-doped siliconoxide layer 14 between the interlayer insulating layer 1 and Si wafer13. The nitrogen-doped silicon oxide layer 14 precludes moisturesupposed to be contained in the Si wafer 13 from penetrating into theFSG layer 1.

[0052] In addition, it is more desirable to form a nitrogen-dopedsilicon oxide layer between the interlayer insulating layer 1 and thefirst silicon nitride layer 4 (Cu diffusion preventive layer). In thiscase, the nitrogen-doped silicon oxide layer improves the adhesionstrength between the interlayer insulating layer 1 and the first siliconnitride layer 4.

[0053] Next, as shown in FIG. 2B, a first nitrogen-doped silicon oxidelayer (hereinafter noted SiON layer) 5 is formed on the first siliconnitride layer 4.

[0054] The SiON layer 5 is formed by means of a parallel plate CVDsystem, for example, shown in FIG. 3. In FIG. 3, denoted at 20 is areaction chamber made of metal such as aluminum (Al). Formed at the topof the reaction chamber 20 is a source gas inlet 21 to introduce sourcegas such as SiH₄, SiF₄, N₂O, N₂ and NH₃ into the chamber. The source gasis controlled in flow rate with a massflow controller (MFC) (not shown),and dispersed uniformly through a gas dispersion plate 22, and suppliedinto the reaction chamber 20.

[0055] The gas dispersion plate 22 serves also as a radio frequency (RF)electrode, and is connected to one end of a radio frequency (RF) powersupply 23. The other end of the RF power supply 23 is grounded. Bysupplying electric power to the RF power supply 23, capacitive couplingoccurs, and electric power is supplied to the space in the reactionchamber 20, and plasma is produced.

[0056] A substrate grounding electrode 24 can hold an Si wafer 25 as asusceptor, and is supported by a lift mechanism so as to control thedistance between the S-wafer 25 and the gas dispersion plate 22 whichacts as an upper electrode. Further, the substrate grounding electrode24 includes a heater 26 to control the temperature of the Si wafer 25 upto about 450° C.

[0057] Also connected to the reaction chamber 20 is a dry pump 27 whichevacuates the chamber 20 and regulates the pressure in the chamber 20through a throttle valve 28.

[0058] Description will now be given on the method of creating an SiONlayer 5 by using the aforementioned parallel plate CVD system.

[0059] First, an Si wafer 25 is introduced into the reaction chamber 20,and held on the substrate grounding electrode 24. Next, source gas, forexample, SiH₄ gas of 50 SCCM, N₂O of 500 SCCM and N₂ of 3000 SCCM areled into the reaction chamber 20, and then the pressure in the chamber20 is regulated to approximately 400 Pa (=3 torr). And, when thepressure and gas flow rate become stable, electric power of 350 watts issupplied to the RF power supply 23. An SiON layer 5 with a thickness of10-100 nm will be formed.

[0060] Next, as shown in FIG. 2B, an FSG layer 6 is formed on the SiONlayer 5. A concrete method of forming the FSG layer 6 will be explainedbelow.

[0061] First, an Si wafer 25 is placed in and held on the substrategrounding electrode 24 in the reaction chamber 20 of the parallel plateCVD system shown in FIG. 3. Next, source gas, for example, SiH₄ gas of100 SCCM, N₂O of 2500 SCCM and SiF₄ of 200 SCCM are introduced into thereaction chamber 20, and then the pressure in the chamber 20 isregulated to approximately 667 Pa (=5 torr). And, when the pressure andgas flow rate become stable, electric power of 1500 watts is supplied tothe RF power supply 23. An FSG layer with a fluorine density of 4-12atomic % and thickness of 100-1500 nm will be formed to match a desiredinterlayer thickness.

[0062] Finally, a second SiON layer 7 is formed on the FSG layer 6. Aconcrete method of forming the SiON layer 7 will be explained below.

[0063] First, an Si wafer 25 is placed in and held on the substrategrounding electrode 24 in the reaction chamber 20 of the parallel plateCVD system shown in FIG. 3. Next, source gas, for example, SiH₄ gas of50 SCCM, N₂O of 500 SCCM and N₂ of 3000 SCCM are introduced into thereaction chamber 20, and then the pressure in the chamber 20 isregulated to approximately 400 Pa (=3 torr). And, when the pressure andgas flow rate become stable, electric power of 350 watts is supplied tothe RF power supply 23. An SiON layer 7 with a thickness of 200-300 nmwill be formed.

[0064] Next, as shown in FIG. 2C, an interlayer insulating layer for asilicon nitride layer 4, SiON layer 5, FSG layer 6 and SiON layer 7 isprocessed by known photolithography and reactive ion etching (RIE),thereby forming an interconnection groove 8 on the surfaces of theinterlayer insulating layers 4-7, and a via hole 9 is formed to connectthe bottom of interconnection groove 8 to the surface of Cuinterconnection 3. The interconnection groove 8 runs through the SiONlayer 7, and the bottom of the interconnection groove 8 presents in theFSG layer 6.

[0065] No particular order is specified in forming the interconnectiongroove 8 and via hole 9. When the via hole 9 is formed first, aphotoresist pattern having a window for the via hole 9 shall be formedon the SiON layer 7, and through this pattern as a mask, reactive ionetching (RIE) is enforced on the interlayer insulating layers 4-7,whereby a via hole 9 is formed. Next, the above photo resist pattern isstripped off, a resist pattern having a window for the interconnectiongroove 8 is formed on the SiON layer 7, and through this pattern as amask, reactive ion etching (RIE) is performed on the FSG layer 6 andSiON layer 7, whereby an interconnection groove 8 is formed.

[0066] Next, as shown in FIGS. 2C and 2D, a second barrier metal layer10 is deposited to cover all over the surface of the interconnectiongroove 8 and via hole 9, and a via plug and Cu layer 11 as aninterconnection layer are formed so as to fill up the interior in theinterconnection groove 8 and via hole 9.

[0067] A second barrier metal layer 10 is formed by sputtering or metalorganic CVD (MOCVD), for example. The Cu layer 11 is, on the other hand,is formed by forming a Cu thin film as a plating seed by the sputteringtechnique, and a Cu film, as interconnection itself, is piled up to adesired thickness on the Cu thin film by using a plating technique.

[0068] Finally, as shown in FIG. 2E, the Cu layer 11 and barrier metallayer 10 formed outside the interconnection groove 8 and via hole 9 areremoved by chemical mechanical polishing (CMP) to flatten the surface ofthe structure. The thickness of residual Cu layer 11 is 200-1000 nm. Inthis way, a second interconnection (upper interconnection layer) 11 andan inter-line via plug which electrically connects the first Cuinterconnection 3 to the second Cu interconnection 11 are completed. Inthis arrangement, the Cu interconnection 11 is dual damasceneinterconnection, but it may also be so called single damasceneinterconnection. Likewise, the Cu interconnection 3 may be either dualdamascene interconnection or single damascene interconnection. In theCMP based process of removing the Cu layer 11 and barrier metal layer 10formed outside the interconnection groove 8 and via hole 9, consideringa polishing margin and the like on the wafer surface, it is allowable toremove a part of the SiON layer 7.

[0069] Thereafter, as shown in FIG. 2F, a second silicon nitride layer12, as a Cu diffusion preventive layer, is formed on the SiON layer 7,barrier metal layer 10 and Cu interconnection 11.

[0070]FIGS. 4B and 5B graphically show diffusion profiles of Si, H, Fand O, respectively, when a specimen not including SiON layer (priorart) and a specimen including SiON layer (the embodiment discussed here)are heated for 2 hours in an annealing furnace at 450° C. in atmosphereof N₂ gas at atmospheric pressure. In this time, the refractive indexesof SiON layers 5 and 7 measured with a He—Ne laser of 633 nm are 1.52.FIGS. 4A and 5A show sectional views of these specimens, respectively.In these figures, the same reference numbers are given to the samecomponents as those in FIG. 2.

[0071] With the specimen not including SiON layers 5 and 7 (FIGS. 4A and4B), pile-up of high concentration F is seen in the interfaces betweensilicon nitride layers 4/12 and FSG layer 6. This is caused by that freefluorine (F) contained in the FSG layer 6 moves to the interfaces duringthe heating process.

[0072] Conversely, with the specimen including SiON layers 5 and 7(FIGS. 5A and 5B), pile-up of high concentration F is not seen in theinterfaces between silicon nitride layers 4/12 and SiON layers 5/7 andthe interfaces between SiON layers 5/7 and FSG layer 6. This is causedby free fluorine (F) contained in the FSG layer 6 diffusing to SiONlayers 5 and 7, which are upper and lower layers, and remains thereon.

[0073] Therefore, according to the first embodiment, free fluorine (F)contained in the FSG layer 6 can be sufficiently absorbed into SiONlayers 5 and 7, and the amount of HF produced as a result of chemicalreaction of fluorine (F) and hydrogen (H) can be substantiallydecreased. This contributes to prevent corrosion of Cu interconnections3/11 and barrier metal layers 2/10 formed on the FSG layer 6. This alsoprevents deterioration of adhesion of the Cu interconnections 11 andbarrier metal layer 10 to the insulating layers 4, 5, 6, 7 and 12, aswell as preventing peeling off of layers during the CMP process in FIG.2E and the processes involving the heating step. The processes involvinga heating step include, for example, annealing to increase grain size inthe Cu interconnections 3/11, heating involved in the step of forming aninsulating layer which is formed after the Cu interconnection 11,annealing to regulate the threshold voltage of MOS transistors, and soon.

[0074]FIG. 6 graphically shows a refractive index of SiON layers 5 and 7measured with an He—Ne laser of 633 nm and a diffusion fluorine layerthickness when heated for 0-20 minutes in an annealing furnace at 450°C. in an atmosphere of N₂ gas at atmospheric pressure.

[0075] It will be apparent from FIG. 6 that when the refractive index ofSiON layers 5/7 is 1.4, namely, the refractive index is low, the Fdiffusion distance increases. This may be caused by surplus freefluorine (F) not being sufficiently absorbed. As the F diffusiondistance increases, the adhesion decreases. On the other hand, it isseen that when the refractive index is 1.50 or higher, the F diffusiondistance becomes sufficiently small. Therefore, it is desirable to setthe refractive index of SiON layer 5/7 to 1.50 or higher.

[0076] In addition, when the refractive index of SiON layers 5/7 ishigh, the permittivity of SiON layers 5/7 increases. This induces theincreased capacitance between interconnections and betweeninterconnection layers, and delays the operating speed of asemiconductor device. Therefore, it is desirable to set the refractiveindex of SiON layers 5/7 to 1.55 or lower.

[0077]FIG. 7 graphically shows a relationship between the refractiveindex and N composition of an SiON layer, which is determined by X-rayphotoelectron spectroscopy (XPS). It is seen from FIG. 7 that therefractive index 1.50 corresponds to the N composition 6 and the index1.55 corresponds to the N composition 10.5 (atomic %), respectively.Therefore, to produce an SiON layer with a refractive index 1.50-1.55,it is necessary to create an SiON layer with a nitride density of 6-10.5atomic % by controlling nitride or other materials used.

[0078] Thereafter, the steps of forming the interlayer insulating layers5-12, barrier metal layer 10 and Cu interconnection 11 are repeated tocreate a multilayer Cu interconnection comprising 4 to 8 layers, wherebythe adhesion between of the Cu interconnection 11 and barrier metallayer 10 to the interlayer insulating layers 5-12 is improved, and asemiconductor device with ensured heat stability and mechanical strengthis realized.

[0079] (Second Embodiment)

[0080] FIGS. 8A-8D are sectional views illustrating a method ofmanufacturing a multi-layer Cu interconnection according to a secondembodiment. In these figures, like reference numerals indicatecorresponding parts in FIGS. 2A-2F, and detail explanation is omitted.Only the difference of the second embodiment from the first embodimentis that a second SiON layer 7 is present during manufacturing, but iseliminated in the final structure.

[0081] First, as shown in FIG. 8A, SiON layer 5, FSG layer 6 and SiONlayer 7 are formed on a first silicon nitride layer 4, as in the firstembodiment. Method, system and conditions for forming these layers 5-7are the same as those in the first embodiment, except the thickness ofSiON layer 7 is 50-100 nm while 200-300 nm in the first embodiment.

[0082] Next, as shown in FIG. 8B, the interconnection groove 8, via hole9, barrier metal layer 10 and Cu layer 11 are formed, as in the firstembodiment. As the SiON layer 7 is 50-100 nm thick, it is easy, ascompared with the first embodiment, to process the insulating layerwhich forms the interconnection groove 8 and via hole 9, and theembedding of Cu layer 1 into the interconnection groove 8 and via hole 9is also easy.

[0083] Next, as shown in FIG. 8C, the Cu layer 11, barrier metal layer10 and SiON layer 7 formed outside the interconnection groove 8 and viahole 9 are removed by the CMP technique to flatten the surface of thestructure. As the SiON layer 7 is as thin as 50-100 nm, the removal ofthis layer is easy.

[0084] Next, as shown FIG. 8D, silicon nitride layer 12 is formed on FSGlayer 7, barrier metal layer 10 and Cu interconnection 11. After this,as in the first embodiment, the steps of forming the interlayerinsulating layers 5-12, barrier metal layer 10 and Cu interconnection 11are repeated to create a multi-layer Cu interconnection comprising 4 to8 layers.

[0085] In accordance with the present embodiment, unwanted capacitanceincrease between interconnections or between interconnection layers canbe effectively suppressed. Additionally, the same effects as in thefirst embodiment can be obtained. The SiON layer 7 may be omitted unlesspeeling-off due to moisture absorption after being left is expected.

[0086] The invention is not to be limited by the embodiments describedherein. For example, in the embodiments, Cu interconnection isdiscussed, but it may alternatively be Al or another metalinterconnection.

[0087] Note that Al interconnection processed by RIE is surrounded bySiON with high permittivity, and if spacing in adjacent interconnectionsis limited, the interline effective permittivity (Keff) becomesrelatively high. Therefore, when spacing is limited in theinterconnections, it is advantageous from the viewpoint of interlinepermittivity to employ Cu damascene interconnection whose upper surfaceis covered by an SiON layer or SiN layer.

[0088] Further, as a diffusion preventive layer, a silicon carbide layermay be used instead of a silicon nitride layer. Also, the Si wafer maybe replaced by other semiconductor wafers such as SOT and SiGe wafers.

[0089] As described in detail above, the present invention realizes asemiconductor device which includes a multi-layer interconnectionemploying a fluorine-doped silicon oxide layer as an insulating layerbetween interconnections to reduce the influence of HF, and a method ofmanufacturing the same.

[0090] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor substrate; an interlayer insulating layer formed abovesaid semiconductor substrate; a first metal interconnection embedded insaid interlayer insulating layer with a surface thereof exposed tosubstantially the same plane as a surface of said interlayer insulatinglayer; a diffusion preventive layer formed on at least said first metalinterconnection to prevent diffusion of a metal included in said firstmetal interconnection; a nitrogen-doped silicon oxide layer formed onsaid diffusion preventive layer; a fluorine-doped silicon oxide layerformed on said nitrogen-doped silicon oxide layer; and a second metalinterconnection embedded in said fluorine-doped silicon oxide layer witha surface thereof exposed to substantially the same plane as a surfaceof said fluorine-doped silicon oxide layer, and electrically connectedto said first metal interconnection.
 2. The semiconductor deviceaccording to claim 1, wherein a refractive index of said nitrogen-dopedsilicon oxide layer is 1.50 or more, and 1.55 or less.
 3. Thesemiconductor device according to claim 1, wherein a nitrogenconcentration of said nitrogen-doped silicon oxide layer is 6 atomic %or more, and 10.5 atomic % or less.
 4. The semiconductor deviceaccording to claim 1, further comprising another diffusion preventivelayer formed on at least said second metal interconnection to preventdiffusion of a metal included in said second metal interconnection. 5.The semiconductor device according to claim 1, wherein said second metalinterconnection comprises a plug with a predetermined width and aninterconnection with a width different from said predetermined width. 6.The semiconductor device according to claim 1, wherein said interlayerinsulating layer comprises a fluorine-doped silicon oxide layer.
 7. Asemiconductor device, comprising: a semiconductor substrate; aninterlayer insulating layer formed above said semiconductor substrate; afirst metal interconnection embedded in said interlayer insulating layerwith a surface thereof exposed to substantially the same plane as asurface of said interlayer insulating layer; a diffusion preventivelayer formed on at least said first metal interconnection to preventdiffusion of a metal included in said first metal interconnection; afirst nitrogen-doped silicon oxide layer formed on said diffusionpreventive layer; a fluorine-doped silicon oxide layer formed on saidfirst nitrogen-doped silicon oxide layer; a second nitrogen-dopedsilicon oxide layer formed on said fluorine-doped silicon oxide layer;and a second metal interconnection embedded in said fluorine-dopedsilicon oxide layer with a surface thereof exposed to substantially thesame plane as a surface of said second nitrogen-doped silicon oxidelayer, penetrating through said second nitrogen-doped silicon oxidelayer, and electrically connected to said first metal interconnection.8. The semiconductor device according to claim 7, wherein a refractiveindex of said first and said second nitrogen-doped silicon oxide layersis 1.50 or more, and 1.55 or less.
 9. The semiconductor device accordingto claim 7, wherein a nitrogen concentration of said first and saidsecond nitrogen-doped silicon oxide layers is 6 atomic % or more, and10.5 atomic % or less.
 10. The semiconductor device according to claim7, further comprising another diffusion preventive layer formed on atleast said second metal interconnection to prevent diffusion of a metalincluded in said second metal interconnection.
 11. The semiconductordevice according to claim 7, wherein said second metal interconnectioncomprises a plug with a predetermined width and an interconnection witha width different from said predetermined width.
 12. The semiconductordevice according to claim 7, wherein said interlayer insulating layercomprises a fluorine-doped silicon oxide layer.
 13. A semiconductordevice manufacturing method, comprising: embedding an underinterconnection layer in an interlayer insulating layer such that asurface thereof is exposed to substantially the same plane as a surfaceof said interlayer insulating layer; forming a diffusion preventivelayer to prevent diffusion of a metal included in said underinterconnection layer, on at least said under interconnection layer;forming a first nitrogen-doped silicon oxide layer on said diffusionpreventive layer; forming a fluorine-doped silicon oxide layer on saidnitrogen-doped silicon oxide layer; forming an interconnection grooveand a via hole extending from a bottom of said interconnection grooveabove said under interconnection layer in said fluorine-doped siliconoxide layer; and forming a plug in said via hole with a metal layer, tobe in electrically contact with said under interconnection layer, and anupper interconnection layer in said interconnection groove with saidmetal layer, to be electrically contact with said plug.
 14. Thesemiconductor device manufacturing method according to claim 13, whereinsaid forming a first nitrogen-doped silicon oxide layer on saiddiffusion preventive layer includes setting a refractive index of saidfirst nitrogen-doped silicon oxide layer to be 1.50 or more and 1.55 orless.
 15. The semiconductor device manufacturing method according toclaim 13, wherein said forming a first nitrogen-doped silicon oxidelayer on said diffusion preventive layer includes setting a nitrogenconcentration of said first nitrogen-doped silicon oxide layer to be 6atomic % or more and 10.5 atomic % or less.
 16. The semiconductor devicemanufacturing method according to claim 13, further comprising forminganother diffusion preventive layer on at least said upperinterconnection layer to prevent diffusion of a metal included in saidupper interconnection layer.
 17. The semiconductor device manufacturingmethod according to claim 13, wherein said interlayer insulating layercomprises a fluorine-doped silicon oxide layer.
 18. The semiconductordevice manufacturing method according to claim 13, further comprising,after said forming a fluorine-doped silicon oxide layer on said firstnitrogen-doped silicon oxide layer, forming a second nitrogen-dopedsilicon oxide layer on said fluorine-doped silicon oxide layer, whereinsaid forming an interconnection groove in said fluorine-doped siliconoxide layer includes forming said interconnection groove to penetratesaid second nitrogen-doped silicon oxide layer.
 19. The semiconductordevice manufacturing method according to claim 18, wherein said forminga plug in said via hole and an upper interconnection layer in saidinterconnection groove includes forming said metal layer on said secondnitrogen-doped silicon oxide layer having said interconnection grooveand said via hole, with a thickness sufficient to fill up an interior ofsaid interconnection groove and said via hole, followed by removing saidmetal layer over said second nitrogen-doped silicon oxide layer.
 20. Thesemiconductor device manufacturing method according to claim 19, whereinsaid forming a plug in said via hole and an upper interconnection layerin said interconnection groove further includes removing said secondnitrogen-doped silicon oxide layer and said metal layer formed over saidfluorine-doped silicon oxide layer, after said removing said metal layerover said second nitrogen-doped silicon oxide layer.